英语翻译The micro-architecture used in our experiment is illustrated in Fig.10.2.Each blockrepresents a micro-architectural module used by our floorplanner.In order to modelperformance more faithfully for modern processors,we isolate and model ea

英语翻译The micro-architecture used in our experiment is illustrated in Fig.10.2.Each blockrepresents a micro-architectural module used by our floorplanner.In order to modelperformance more faithfully for modern processors,we isolate and model ea
英语翻译
The micro-architecture used in our experiment is illustrated in Fig.10.2.Each block
represents a micro-architectural module used by our floorplanner.In order to model
performance more faithfully for modern processors,we isolate and model each wire
as a separate resource which consumes power and has a delay in proportion to its
length.Note that architectural simulators that ignore inter-module communication
latencies will no longer be useful for evaluating high frequency processors designed
with nano-scale technologies due to wire delays,floorplan constraints,and thermal
concerns.Essentially,the inter-module latency is a function of the distance and
the number of flip-flops between modules and must be taken into account in both
performance evaluation and floorplanning.For this reason,we use the distances
generated by the floorplanner to determine the latency-related parameters such
as pipeline depth and communication/forwarding latencies for our performance
simulation.
The micro-architectural configuration used in our study1 is summarized as
follows:the machine width is 8.We use a 1,024-entry gshare branch predictor,
a 512-entry register update unit (RUU) [45] that combines the functionality of a
reservation station and a reorder buffer,16KB instruction and data L1 caches,a
256KB unified L2 cache and no L3 cache,128-entry instruction and data TLBs,8
ALUs,4 FPUs,and a 64-entry load store queue.

英语翻译The micro-architecture used in our experiment is illustrated in Fig.10.2.Each blockrepresents a micro-architectural module used by our floorplanner.In order to modelperformance more faithfully for modern processors,we isolate and model ea
在我们的实验中使用的micro-architecture见图10.2.每一块
　　代表我们floorplanner micro-architectural模块使用.为了模型
　　为现代处理器性能更忠实,我们每个线隔离和模型
　　作为一个单独的资源消耗能源和延迟其比例
　　长度.注意,体系结构模拟器,忽略inter-module沟通
　　延迟将不再有用的评价高频处理器设计
　　与加载存储队列和64条目.